Typically, a phase locked loop (PLL) circuit having a wide loop bandwidth, has an advantage in that tolerance for external noise is strong and PLL control can be performed with high precision in a wide band. In a case where the loop bandwidth of the PLL circuit is designed to be wide, minimizing delay time of a loop is important in order to secure a phase margin, sufficiently.
However, delay time tends to increase due to a lock circuit that performs phase error calculation and filter processing, in a digital PLL circuit. Therefore, a configuration having a wideband PLL circuit has been proposed by adding a phase frequency detector (PFD) and an analog filter to generate a low delayed signal path.
However, a problem occurs that a circuit area and power consumption increase when the phase frequency detector and the analog filter, both including analog elements, are added inside the digital PLL circuit. Another problem occurs that calibration is required, before operation of the digital PLL circuit, in order to prevent a filter characteristic from shifting from a desired value due to a variation of an electrical characteristic of the analog element, and thus time and labor are required for maintenance. Accordingly, it takes time to operate the digital PLL circuit and a further increase of the power consumption occurs.